1. Field of the Invention
The present invention relates to a digital filter and particularly to a digital filter receiving an analogue signal as an input.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a construction of a conventional finite impulse response (referred to hereinafter as FIR) type digital filer disclosed for example in "Theory and Application of Digital Signal Processing" by L. R. Rabiner and B. Gold, 1975, Prentice-Hall, Inc., pp. 40-51. An analogue signal inputted from an input terminal 1 is converted to a binary digital signal by an A-D converter 2. An output of the A-D converter 2 is supplied to a digital filter 3. The digital filter 3 comprises delay elements 4a to 4c, multipliers 5a to 5d and adders 6a to 6c so that multiplication and addition operations of digital signals are performed. The delay elements 4a to 4c delay the respective inputs thereof by one sample cycle, the delay elements 4a to 4c being connected dependently on the output of the A-D converter 2. The multipliers 5a, 5b, 5c and 5d receive, as a first input, the output of the A-D converter 2, an output of the delay element 4a, an output of the delay element 4b and an output of the delay element 4c, respectively, and receive, as a second input, digital signals A, B, C and D, respectively. The multipliers 5a to 5d each multiply the first and second inputs. Thus, if the above stated digital signals A, B, C and D are changed, filtering characteristics of the digital filter 3 can be changed. The adders 6a, 6b and 6c receive, as a first input, an output of the multiplier 5b, an output of the multiplier 5c and an output of the multiplier 5d, respectively, and receive, as a second input, an output of the multiplier 5a, an output of the adder 6a and an output of the adder 6b, respectively. The adders 6a to 6c each adds the first and second inputs, so that an output of the adder 6c is provided as an output of the digital filter 3.
In the example shown in FIG. 1, a transfer function H(z) of the digital filter 3 is represented by the below indicated equation (1). EQU H(z)=A+BZ.sup.-1 +CZ.sup.-2 +DZ.sup.-3 ( 1)
where Z.sup.-n represents a delay in the "n"th sample cycle (n being an integer).
Assuming that an input data group X of the digital filter 3 is represented by the below indicated equation: EQU X={x(0), x(1), x(2), x(3), . . . },
an output data group Y is as follows: ##EQU1## As a result, z-transforms of the input data group X and the output data group are represented as follows: ##EQU2## Thus, a digital output according to the transfer function H(z) is obtained.
In the conventional digital filter thus constructed, the A-D converter 2 is required if the input signal is an analogue signal. Conventionally, the A-D converter 2 is provided on a chip different from that of the digital filter 3 and, accordingly, the size of the apparatus is increased. In addition, since the multipliers 5a to 5d multiply binary digital signals, they are formed by using full adders and, as a result, a carry delay occurs in the multipliers, which causes operation speed of the digital filter to be slow. Such problems become more serious according to increase of the number of bits of digital signals to be processed. In order to increase a multiplication speed, the multipliers may be formed as a pipeline. However, such method causes the construction of the apparatus to be further complicated and the size of the apparatus to be increased.